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Eric C. Maass

(602)-494-9045 (Home)



Business / P & L Experience

Operations Manager , Wireless Transceiver Products, Motorola SPS. Responsible for P & L, business decisions, strategic direction, new product development. Direct efforts of 45 engineers (product, design, test).

Operations Manager, High Performance and Communication Products. Directed efforts of 32 design, product, and test engineers developing high frequency/RF new products. Introduced 40 ECLinPS-Lite (E-Lite) products and 60 communication products in 3.5 yrs, including a GPS receiver, prescalers, VCO's, synthesizers, fiber optics, wired communication (Autobahn), and parallel fiber optics (Optobus). Quadrupled sales, achieved 35% PBT.

Cost Reduction Manager, Logic I.C. Division. Coordinated and institutionalized cost reduction efforts in operations, wafer fab and assembly manufacturing areas which resulted in an increase in PBT from <5% to >15%.

Wafer Fab Experience

Device Engineering Manager, Bipolar 2 Wafer Fab. Managed 20 engineers, reduced die loss 50% to 80% in product families, achieved 93% yield. Led edge-die inking, Wafer Level Reliability

Device Section Manager, Bipolar 1 Wafer Fab.. Improved yields 15% on Analog products. Brought up Power BiMOS process (Sector Top 10 project), helped develop SmarTMOS process. Instituted hot/cold wafer probe process . Acting Device Engineering Manager Special MEIP Award.

SPC Consultant, RF Division. At request of Vice President, led SPC and process improvement efforts in RF Wafer Fab. Led team efforts to reduce Beta variability, improve photo/etch, TiW integrity, and resolve TMOS Vt instability.

Team Leadership / Problem Solving

Team Leader, FACT TOPS Team. Won Gold Medal in Corporate T.C.S., top award among 5000 teams; selected to exemplify teamwork and problem solving in Motorola Corporate training videotape, "Team Problem Solving the Motorola Way". Improved 1.5u CMOS yield 40%, on-time delivery 88%, and achieved record new product introductions.

Team Leader, ECLinPS TOPS Team. Won Silver Medal in Sector T.C.S. Improved ESD from <500 to > 4000 V on advance bipolar product, improved yield and robustness.

Research and Development Experience

Developed "Technology Development Process" for Sector R & D efforts; used process to propose the exploration of GCMOS for RF applications.

Brought up Power BiMOS process (Sector Top 10 project), helped develop SmarTMOS process .

CMOS Process Development: Introduced 3u HCMOS into production. Improved 5u CMOS yields from 30 to 70%. Produced first functional 1u CMOS devices (1979). Special MEIP Award.

Bipolar Process Development: Improved analog product yields from 25% to 75% by implementing improved resistor, base, and JFET structures/processes. Developed field guard isolation process for MOSAIC I (FAST and MECL10H).

Manager, Process Information System, MICARL. Set up first system in Motorola incorporating process, PC probe, and 100% Probe information in a common database. (1982 to1983).

Communication Skills

Developer and Master Instructor for course "Introduction to Logic and Computer Design". Also, developed and instructed courses in Semiconductor Processing, Process Simulation, Yield Surface Modeling, and Statistics Decision Tree. Developed statistical software for the course (VCA, Gauge Capability, RSM, and YSM).

Invited Speaker, Total Quality Forum (audience consisted of Deans of top universities, business leaders).

PUBLICATIONS and PATENTS:

Coeditor, Handbook of Optoelectronics for Data Communication, Academic Press, Summer, 1997.

"Integrating Voice Recognition Technology with Inspection of I.C.'s", Proceedings of the Intl. Semiconductor Manuf Science Symp, May,90.

"System Moments Method for Reducing Fabrication Variability", Solid State Technology, August, 1987.

"A Strategy for Reducing Variability in a Production Semiconductor Fabrication Area Using the Generation of System Moments Method", Emerging Semiconductor Technology, ASTM, 1987.

"Three Micron Silicon Gate CMOS Process", Correlations, 1982.

Developed a new statistical method to optimize yield for multiple output characteristics simultaneously, Yield Surface Modeling. First software patent applied for within Motorola, patent #5,438,527.

Developed a copper inductor structure on silicon with Q>20 @1GHz. (Note: AT&T issued a press announcement a year later for achieving a Q of 10). Named the top "Eureka Fund" project for SPS. Patent # 5,478,773.

EDUCATION:

Master of Science in Chemical Engineering, Arizona State University,1982. 3.62 GPA. Thesis: A Mathematical Simulation of a Thin-Film Thermal Enzyme Probe. This became "... the first major technology transfer involving ASU researchers and a commercial company...' when the sensor was licensed to Boehringer Mannheim.

Working towards PhD in Industrial and Management Systems Engineering. Proposed dissertation topic: Optimization of On-Time Delivery, Inventory, and Lead-time Tradeoffs.

Member, Phi Kappa Beta.